1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a standard cell or an embedded array.
2. Related Art
Semiconductor devices have been widely used in various fields of household electric appliances and developments of semiconductor integrated circuits for specific appliances have been strongly demanded. For this purpose, in recent years, an ASIC (Application Specific Integrated Circuit) technology has intensively been developed.
In the ASIC technology, two types of technology are employed, one is a standard cell system and the other is an embedded array system. The standard cell system has features of a high degree of integration and flexibility in design, and the embedded array system has a feature of a short development term in addition to the features of the standard cell system.
In either of the systems, in order to obtain higher integration, it is necessary to decrease area of interconnections while maintaining the flexibility in design.
There have been used two major methods for connecting a power terminal and a ground terminal to a semiconductor integrated circuit having a plurality of cores of ROMs and/or RAMs, etc.
These conventional connection methods will be explained in the following description with reference to FIGS. 1-5. It is to be noted that hereinafter the same parts will be indicated by the same reference numerals and their repeating explanations will be omitted.
The first method is a direct connection of the power and ground terminals to I/O cells of a core. FIG. 1 is a plan view showing this method. As shown in FIG. 1, power terminals 101a, 101b, 102a and 102b connected to an I/O cell in a core 1 are provided at peripheral sides of the core 1, and V.sub.DD and V.sub.SS are supplied to the power terminals. In this method, however, flexibility in design will be remarkably decreased since locations of the power terminals are fixed.
The second method is to dispose two interconnecting conductors in the peripheral part of the core to surround the core, with each of the conductors being connected to V.sub.DD and V.sub.SS. FIG. 2 is a plan view for explanation of this method. Such configuration of the interconnections will be referred to "ring-shaped" hereinafter. Referring to FIG. 2, there are provided a first surrounding interconnection 111 around the core 1 and a second surrounding interconnection 112 around the first surrounding interconnection 111. V.sub.DD and V.sub.SS are supplied to these interconnections 111 and 112, respectively. The interconnections 111 and 112 are formed in the same layer, and for example, the interconnection 111 is connected to the core 1 via a coupling conductor (not shown in FIG. 2) formed in the same layer and lower layer and the interconnection 112 is connected to the core 1 via a coupling conductor formed in upper layer or lower layer. Thus by using ring-shaped interconnections, connections of power supply V.sub.DD and V.sub.SS to interconnections can be performed at any side, which results in improved flexibility in design.
This second method indeed improves flexibility in design when compared to the first method shown in FIG. 1, however, the second method requires additional area for arranging interconnections 111 and 112 which decreases the degree of integration. Since in the ASIC technology, a chip generally includes a plurality of cores, which require additional area for connections with power supplies of the plurality of cores, and therefore the integration of the whole device is remarkably decreased.
FIG. 3 shows a plan view of the semiconductor integrated circuit device 120 having two cores, to which the method shown in FIG. 2 is applied. As shown in FIG. 3, two cores 1 and 2 are respectively provided with interconnections 111 surrounding each core and the interconnections 112 surrounding the interconnections 111, respectively. This arrangement needs an area for 4 interconnections between the core 1 and the core 2, which results in decrease in integration of the semiconductor device.
Furthermore, as shown in FIG. 4, in the case where a semiconductor integrated circuit device 140 has three or more cores (cores 1, 2 and 3) arranged in matrix form, areas for interconnections are necessary between neighboring cores in both x-direction and y-direction, which will remarkably decrease the integration of the device.